The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down has also increased the complexity of processing and manufacturing ICs.
ICs are typically fabricated by processing semiconductor wafer 5ith a series of wafer fabrication tools (i.e., “processing apparatus”). Each processing apparatus typically performs a single wafer fabrication task on the semiconductor wafer. For example, a chemical mechanical polishing (CMP) apparatus is used for performing a polishing process for planarization of semiconductor wafers. The polishing processes may be used to form planar surfaces on dielectric layers, semiconductor layers, and conductive material layers of a wafer, for example.
Although existing CMP systems have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. Consequently, it would be desirable to provide a solution to improve the CMP systems so as to mitigate or avoid the production of excess scrap wafer due to defects formed during the polishing process.